The delay computation process for an integrated circuit requires knowledge of ramp time and loading at each stage. The loading can be determined by picking up a stage and its driven net. However, the ramp time has to be determined through propagation of calculations through preceding stages.
The delay of a cell typically depends at least in part on the ramp time and the output loading. In a given integrated circuit design, the signal can propagate through several stages before being captured by a flip flop. The order of the signal propagation defines the order in which the delays are computed in the circuit. Thus, a two pin AND gate typically has ramp times that are computed for both its inputs before its delays are completely evaluated.
This implies that the stage after the AND gate, for example, is typically completely evaluated only after the AND gate has been completely evaluated. This creates a motivation to have a topological order for the circuit before computing the delays.
The various embodiments of the present invention can be used to reduce the run time of a delay calculation and static timing analysis. In addition, the embodiments can be used to support efficient timing updates in a static timing analyzer.